1. Field of the Invention
The present invention generally relates to clock synchronization type semiconductor memory integrated circuits and, more particularly, to an improvement of an address decoding circuit.
2. Related Background Art
FIG. 14 shows a block diagram of a prior art clock synchronization type semiconductor memory integrated circuit. An external clock signal CLK is inputted to a clock buffer 4, in which internal clock signals CK1 and CK2 are generated. Address signals are inputted to an address buffer 8 in sync with the clock signals CK1, among which a row address signal is sequentially decoded by a predecoder 6 and a row decoder 7 to select a word line WL of a memory cell array 1.
The internal clock signal CK2 from the clock buffer 4 and a timing pulse PULSE generated at a pulse generating circuit 5 based on the internal clock signal CK1 are sent to the predecoder 6. The timing pulse PULSE is used for adjusting a transfer timing of a predecoded output PD1 to the row decoder 7.
A column address is decoded by a column decoder 9. Based on the decoded output from the column decoder 9, a column gate 3 is selectively driven to select a bit line of the memory cell array 1. Data of a memory cell MC determined by the selected word line WL and the selected bit line BL is read out to the bit line BL, sensed and amplified by a sense amplifier 2, and outputted via a data buffer 10.
In a large-scale semiconductor memory circuit, the memory cell array 1 is divided into a plurality of memory sections 1-1 to 1-n, as shown in FIG. 15. A main word line MWL is shared by the memory sections 1-1 to 1-n, and a plurality of word lines WL, each corresponding to one of the memory sections, are selectively connected to the main word line MWL in accordance with section selection signals SSL1 to SSLn.
FIG. 16 shows an example of a specific configuration of the row address decoding system (word line selecting system) shown in FIG. 14. The address buffer 8 includes a latch circuit (master latch), having inverters INV 4 and INV 5, for temporally holding address data inputted in sync with the clock signal CK1. In order to carry out a grouping selection of a plurality of main word lines MWL, the predecoder 6 includes a predecoding section 6a for selecting one line from a bundle of main word lines MWL, and a predecoding section 6b for selecting a bundle of main word lines MWL.
The predecoding sections 6a and 6b have NAND gates NAND1 and NAND3, respectively, for decoding an internal address A0 sent from the address buffer 8 in accordance with the clock signal CK2. Further, the predecoding sections 6a and 6b have latch circuits (slave latches) formed of inverters (INV9, INV10) and (INV13, INV14), respectively. The decoded output latched by the predecoding section 6a is taken from a NAND gate NAND 2 and sent to the row decoder 7 as an output PD1. The latch data of the other predecoding section 6b is sent to the row decoder 7 as an output PD2 via inverters INV15 and INV16 without being adjusted by the timing pulse.
The pulse generating circuit 5 generates a timing pulse PULSE in consideration of the number of logical circuits (delays) provided before the predecoder 6 decodes an address externally received. Specifically, in the example shown in FIG. 16, odd-number inverters INV24 to INV26 and a NAND gate NAND5 form an edge detecting circuit 51 for detecting a rising edge of the internal clock signal CK1, and even-number inverters INV28 to INV31 and a NOR gate NOR1 form a pulse width setting circuit 52 for determining a pulse width. Therefore, the pulse generating circuit 5 generates, in sync with a rising of the clock signal CK1, a timing pulse PULSE having a pulse width determined by the delays of the inverters INV28 to INV31.
The row decoder 7 includes a NAND gate NAND4 for further decoding the predecoded output PD2 and transfer gate transistors M1 and M2, which are controlled by the output of the NAND 4 and transfer the predecoded output PD1 to the main word line MWL. In more detail, in the row decoder, when the prededecoded output PD2 is inputted (all 1""s), the output of the NAND gate NAND4 becomes xe2x80x9cLxe2x80x9d, thereby turning on the transfer gate transistors M1 and M2 to supply the predecoded output PD1 to the main word line MWL.
FIG. 17 shows the timings in the above described row address decoder from the input of the external clock signal CLK to the activating of a word line. A timing pulse PULSE is generated so as to have a predetermined pulse width in which the predecoded outputs PD1 and PD2 are accomplished. Thus, the predecoded outputs PD1 and PD2 are further decoded by the row decoder 7, and the selection of a main word line MWL and a selection of a word line ML are carried out. In addition, in the row decoder 7, three inverters INV18 to INV20 inserted after the transfer gate transistors M1 and M2 are for the purpose of waveform formation, because an xe2x80x9cHxe2x80x9d level attenuation occurs in the transfer gate transistors M1 and M2, and the signal level is not fully compensated by only a single inverter. After a main word line MWL is selected, a word line WL is selected by a NOR gate NOR2 activated by a section selection signal SSL.
In the prior art clock synchronization type address decoder shown in FIG. 16, it is preferable to reduce the delay determined by the number of the logical circuits in the address buffer 8 and the predecoder 6, and to speed up the rising of a timing pulse PULSE generated by the pulse generating circuit 5 as much as possible. Since these sections are already formed of a minimum number of logical circuits, it is difficult to remarkably speed up the operations of these sections unless it is possible to reduce the delay of each logical circuit.
In the circuit arrangement shown in FIG. 16, it is rather the number of logical circuits needed to be used after the generation of the timing pulse PULSE until the selection of a word line WL that is preventing the speeding up of the operations. In FIG. 16, if the transfer gate transistors (M1, M2) are assumed to be a single logical circuit, the number of the logical circuits after the generation of the timing pulse PULSE until the selection of a word line WL is seven (NAND2, INV11, (M1, M2), INV18 to INV20, and NOR2). Due to the existence of these logical circuits, a considerable delay is caused before a word line is activated. In FIG. 17, a delay after the rising of the timing pulse PULSE until the activation of the selected word line WL is shown as xcfx842.
Further, as the capacities of semiconductor memories increase, if the number of bits in a row system is doubled, the number of row decoder is also doubled, thereby doubling the load per one predecoder. Accordingly, the delays caused by the predecoded outputs PD1 and PD2 are increased. In order to reduce such delays, the size of output buffer in the predecoder, i.e., the size of the inverters INV11 and INV16 in FIG. 16, maybe increased. However, there is a limit to the improvement of input waveform of a row decoder, which causes a large load. Further, there may arise another problem in that the increasing of the size of output buffer may increase power consumption.
Given the above mentioned circumstances, an object of the present invention is to provide a semiconductor memory integrated circuit in which the number of logical circuits needed to be used during a period from the input of a clock signal to the activation of a word line is reduced to speed up operations.
A semiconductor memory integrated circuit according to the present invention comprises: a memory cell array; a clock buffer for receiving a clock signal to generate an internal clock signal; an address buffer for receiving an address signal in accordance with said internal clock signal generated by said clock buffer; an address decoding circuit including a first stage decoder for decoding an internal address signal outputted from said address buffer to select a word line of said memory cell array, and a second stage decoder for further decoding an output of said first decoder to drive a selected word line; and a pulse generating circuit for generating a timing pulse for controlling an activation timing of said second decoder of said address decoding circuit based on the internal clock signal outputted from said clock buffer.
According to the present invention, timings of the first stage decoder of the address decoding circuit are not controlled by the use of clock signals, but timings of the second stage decoder are controlled thereby. Because of this, it is possible to reduce the logical delay caused in a period from the input of a clock signal to the activation of a selected word line, as compared to the prior art systems, thereby speeding up the operations.